Normally off gallium nitride field effect transistors (fet)

ABSTRACT

A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero-junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.

This application is a Continuous application and claims priority of apending application Ser. No. 14/729,396 filed on Jun. 3, 2015 andapplication Ser. No. 14/729,396 is a Divisional application, and claimspriority of another application Ser. No. 13/726,102 filed on Dec. 22,2012 by the common inventors of this application now issued into U.S.Pat. No. 9,064,945 on Jun. 23, 2015. The application Ser. No. 13/726,102is a Divisional application of another application Ser. No. 12/589,945filed on Oct. 30, 2009 and issued into U.S. Pat. No. 8,338,860 on Dec.25, 2012 by the common inventors of this application. The benefit of thefiling dates are hereby claimed under Title 35 of the United StatesCode. The disclosures of application Ser. Nos. 12/589,945, 13/726,102and 14/729,396 are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to the configurations and methods ofmanufacturing the semiconductor devices. More particularly, thisinvention relates to a gallium nitride (GaN)-based field effecttransistor implemented with new device configurations and manufacturingmethods for a normally-off GaN-based field effect transistor that has anextremely small ON resistance in conducting a large amount of electriccurrent.

2. Description of the Prior Art

Conventional methods of configuring and manufacturing a gallium nitride(GaN) based field effect transistors (FETs) are still continuouslychallenged with a technical issue for providing a normally-off FETtransistor that has simple and convenient manufacturing and operatingconfigurations. Specifically, gallium nitride (GaN) based FETs have beenimplemented to make high electron mobility transistors (HEMTs). Forapplications of the power transistors, this type of transistor mayreplace some power devices implemented with powermetal-oxide-semiconductor (MOS) field-effect transistor using asilicon-based semiconductor that are commonly and widely used now.Compared to the silicon-based MOS-FET (or MOSFET) semiconductor powerdevices, the GaN-based transistors can further reduce the on-resistanceand realize higher breakdown voltage by taking advantage of thesemiconductor material characteristic of a wide band-gap. Furthermore,this high electron mobility transistor can also provide high speedswitching and high sensitivity operations relative to the performance ofthe silicon-based MOSFET devices.

The basic principle of achieving the high electron mobility is achievedby bonding two different kinds of semiconductor materials with differentband gaps. A two dimensional electron gas (2DEG) layer is generated atthe interface thus serving as a current path comprising a flow ofelectrons in this electron gas layer. A specific example is illustratedin FIG. 1 with an aluminum gallium nitride (AlGaN) epitaxial grown ontop of gallium nitride (GaN) layer. With different band gaps of thesetwo materials, a two dimensional electron gas layer (2DEG) is generatedin the boundary, referred to as an AlGaN/GaN hetero-junction, betweenthese two semiconductor materials. Typically, the AlGaN/GaNhetero-junction structure is supported on insulating substrate, such asa sapphire substrate. The transistor further includes a source electrodeS and a drain electrode D which are arranged on two opposite sides of agate electrode G formed onto the AlGaN layer that spreads between thesource electrode S and the drain electrode D.

With the AlGaN layer functioning as an electron supply layer andsupplies electrons to the 2DEG in the undoped GaN layer, the electronsin the electron gas layer transmits between the source electrode and thedrain electrode even when there is no control voltage applied to thegate. The high electron mobility transistor (HEMT) configuration as thatshown in FIG. 1 thus operates in a normally-on mode unless a voltage isapplied to the gate to pinch off the current flow between the source andthe drain electrode. A requirement to continuous apply a pinch offvoltage to the gate in order to turn off the transistor thus leads toadditional power consumptions and may often cause a more complicateddevice control process for implementing such transistor in an electronicdevice. In addition most applications are designed for normally-offtransistors and so this device would not be suitable to thoseapplications. For these reasons, it is desirable to provide new andimproved configurations for manufacturing GaN-based transistors suchthat the device is normally-off, without requiring application of apinch-off voltage to the gate.

Most of the AlGaN/GaN heterostructure field effect transistors (HFETs)are provided as depletion mode metal-semiconductor FET (MESFET) in orderto achieve a low on resistance RdsA (drain-to-source resistance*area).Enhancement mode MESFET devices with threshold voltage Vth between 0.3to 0.7 volts have been disclosed. But these types of transistors cannotbe driven by a gate voltage between the traditional gate voltage oftento fifteen volts. Also, various efforts have been attempted to buildenhancement mode metal insulator semiconductor FET (MISFET) on a p-GaNlayer using different gate dielectrics including silicon nitride(Si3N4), silicon oxide (SiO2) and gadolinium oxide (Gd2O3). However,such devices suffer the disadvantages of low inversion mobility and avery high electric field in the oxide when the device is biased into thebreakdown thus causing device reliability concerns. In order to addressthis issue, an oxide layer with increased thickness had beenimplemented, but that degraded the transconductance and lead to anundesirable higher RdsA.

For all these reasons, there are great and urgent demands to improve thedevice structure with low RdsA while not disturbing the conductivity ofthe two-dimensional electron gas (2DEG) layer. In the meanwhile, it isdesirable that the device may be operated as a normally off devicewithout applying a voltage to the gate such that the above-discusseddifficulties and limitations may be resolved.

SUMMARY OF THE PRESENT INVENTION

It is therefore an aspect of the present invention to provide a new andimproved device configuration and manufacturing method to provide aheterostructure field effect transistor (HFET) power device thatprovides simple and convenient manufacturing and operating processes toimplement the HFET device as a normally-off device such that the abovediscussed difficulties and limitations may be resolved.

Specifically, it is an aspect of the present invention to provideimproved device configuration and method for manufacturing asemiconductor GaN-based HFET power device with negatively chargedfloating gate to deplete the channel when no voltage is applied to thegate. The negative charged floating gate is formed by applying a similarprocess as for forming a floating gate commonly implemented in flashmemory, which is a mature and well known technology. A gate voltage isapplied to offset the negatively charged floating gate to restore the2DEG channel formed on the hetero-junction between the GaN and AlGaNlayers.

It is another aspect of the present invention to provide improved deviceconfiguration and method for manufacturing a multiple-channelsemiconductor GaN-based HFET power device with negatively chargedfloating gate formed as wrap-around floating gate to deplete themultiple channels when no voltage is applied to the gate. The negativecharged floating gate is provided by applying a similar process as afloating gate commonly implemented in flash memory. A gate voltage isapplied to offset the negatively charged wrap-around floating gate torestore the 2DEG channels formed on the hetero-junctions betweenmultiple layers of GaN and AlGaN interfaces.

It is another aspect of the present invention to provide improved deviceconfiguration and method for manufacturing a semiconductor GaN-basedHFET power device with negatively charged gate oxide layer to depletethe channel when no voltage is applied to the gate. The negative chargedgate oxide may be provided by fluorine treatment or a similar process todeposit fixed negative charges into the gate oxide layer. A gate voltageis applied to offset the negatively charged gate oxide to restore the2DEG channel formed on the hetero-junction between the GaN and AlGaNlayers.

Briefly in a preferred embodiment this invention discloses aheterostructure field effect transistor (HFET) gallium nitride (GaN)semiconductor power device. The power device comprises a hetero-junctionstructure comprises a first semiconductor layer interfacing a secondsemiconductor layer of two different band gaps thus generating aninterface layer as a two-dimensional electron gas (2DEG) layer. Thepower device further comprises a source electrode and a drain electrodedisposed on two opposite sides of a gate electrode disposed on top ofthe hetero-junction structure for controlling a current flow between thesource and drain electrodes in the 2DEG layer. The power device furthercomprises a floating gate located between the gate electrode andhetero-junction structure, wherein the gate electrode is insulated fromthe floating gate with an insulation layer and wherein the floating gateis disposed above and padded with a thin insulation layer from thehetero-junction structure and wherein the floating gate is charged forcontinuously applying a voltage to the 2DEG layer to pinch off thecurrent flowing in the 2DEG layer between the source and drainelectrodes whereby the HFET semiconductor power device is a normally offdevice. In another embodiment, the first semiconductor layer is agallium nitride (GaN) layer and the second semiconductor layer is analuminum gallium nitride (AlGaN) layer disposed on top of the galliumnitride layer. In another embodiment, the semiconductor power devicefurther includes a sapphire substrate for supporting the hetero-junctionstructure thereon. In another embodiment, the floating gate isnegatively charged to shift a pinch off voltage of the 2DEG layer from anegative pinch off voltage to a positive pinch off voltage. In anotherembodiment, the first semiconductor layer is an N-type gallium nitridelayer and the second semiconductor layer is an N-type AlGaN layerdisposed on top of the gallium nitride layer. In another embodiment, thefloating gate is negatively charged to shift a pinch off voltage of the2DEG layer from a negative pinch off voltage to a positive pinch offvoltage equal to or greater than three volts (3.0V). In anotherembodiment, the source electrode further includes an extended fieldplate extending from the source electrode and covering over the gateelectrode. In another embodiment, the source electrode further includesan extended field plate extending from the source electrode and coveringover the gate electrode wherein the field plate is insulated from thegate electrode with a thick insulation layer. In another embodiment, thehetero-junction structure comprises the first and second semiconductorlayers constituting a rectangular block with a longitudinal directionextending from the source electrode to the drain electrode. And, thegate electrode and the floating gate with the insulation layersconstitute a wrap-around gate wrapping around a middle segment of therectangular block around sidewalls and a top surface of the middlesegment of the rectangular block to control the 2DEG layer generatedbetween the first and second semiconductor layers. In anotherembodiment, the hetero-junction structure comprises the first and secondsemiconductor layers constituting the rectangular block wherein thefirst and second semiconductor layers of two different band gaps arevertically oriented. In another embodiment, the semiconductor powerdevice further includes at least a third semiconductor layer disposedimmediately next to each other with two adjacent semiconductor layershaving two different band gaps for generating at least two interfacelayers as at least two two-dimensional electron gas (2DEG) layers.

These and other objects and advantages of the present invention will nodoubt become obvious to those of ordinary skill in the art after havingread the following detailed description of the preferred embodiment,which is illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is cross sectional view to show a conventional normally-onGaN-based HFET power device.

FIG. 2 is a cross sectional view of a HFET power device of thisinvention with negative charged floating gate to deplete the channel foroperating the transistor as a normally-off device.

FIG. 3 is a cross sectional view of a HFET power device of thisinvention with negative charged gate oxide layer to deplete the channelfor operating the transistor as a normally-off device.

FIG. 4 is a cross sectional perspective view of a multiple-channel HFETpower device of this invention with negative charged floating gateconfigured as wrap-around floating gate to deplete the channel foroperating the transistor as a normally-off device.

FIG. 5 is a top view of the HFET power device of FIG. 4.

FIGS. 6 and 7 are cross sectional perspective views of alternativeembodiments of HFET power devices of this invention similar to that ofFIG. 4.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Referring to FIG. 2 for a cross sectional view of a heterostructurefield effect transistor (HFET) semiconductor power device 100 of thisinvention. The HFET semiconductor power device 100 comprises an AlGaNlayer 120 epitaxial grown on top of gallium nitride (GaN) layer 110 thusforming a AlGaN/GaN hetero-junction with a two-dimensional electron gas(2DEG) 115 located at the interface. The AlGaN/GaN hetero-junctionstructure is supported on a sapphire substrate 105. A source electrode130 and a drain 140 are disposed on two opposite sides of a gateelectrode 150 to control the current flow through the 2DEG layer 115.The gate electrode 150 is insulated from the N-doped AlGaN layer 120with a thicker gate oxide layer 155. In order to configure the HFETpower device as a normally off device, a floating gate 160 is formedbeneath at least a portion of the gate oxide layer 155. The floatinggate 160 is insulated from the AlGaN layer 120 with a thin oxide layer145, and from the gate electrode 150 by gate oxide 155.

The floating gate 160 is negatively charged and is configured to shiftthe pinch off voltage from a negative pinch off voltage to a positivepinch off voltage. For example, the pinch off voltage Vp was originally−4.0 volts without the negatively charged floating gate, is now shittedto a pinch off voltage of +3 volts with the negatively charged floatinggate 160. Without an external applied voltage to the gate electrode 150,the floating gate 160 automatically pinches off the 2DEG 115. The gateelectrode 150 overlaps the negatively charged floating gate 160 and isinsulated from it with a thick oxide layer 155. The gate electrode 150is applied a voltage to control the electric field. The function of thegate electrode 150 is therefore not to invert the channel. The functionof the gate electrode 150 is to cancel the negative charges on thefloating gate 160, which would then allow the 2DEG 115 to formuninterrupted between source 130 and drain 140 and thus turn on thedevice. The negative charges may be injected, e.g., written to thefloating gate 160 in a same manner as charges are written to flashmemory devices.

Referring to FIG. 3 for a cross sectional view of anotherheterostructure field effect transistor (HFET) semiconductor powerdevice 200 of this invention. The HFET semiconductor power device 200has a similar AlGaN/GaN hetero-junction structure with a two-dimensionalelectron gas (2DEG) layer 215 formed at an interface layer between agallium nitride (GaN) layer 210 and AlGaN layer 220. The AlGaN/GaNhetero-junction structure is supported on a sapphire substrate 205. Asource electrode 230 and a drain 240 are disposed on two opposite sidesof a gate electrode 250 to control the current flow through the 2DEGlayer 215. The source electrode 230 is formed with an extended fieldplate 230-FP that extends and covers over the gate electrode 250 toreduce the gate oxide peak field near the drain electrode 240. Theextended field plate 230-FP is insulated from the gate electrode 250 bya thick oxide 235. The gate electrode 250 is insulated from the N-dopedAlGaN layer 220 with a gate oxide layer 255. In order to configure theHFET power device as a normally off device, fixed negative charges arestored, e.g., in the same manner charges are stored in flash memory, inthe gate oxide layer 255 by fluorine treatment into AlGaN layer oralternate processes during the manufacturing process. The negativecharges fixed in the gate oxide layer 255 drive off the electrons in the2DEG layer 215 thus depleting the channel. A voltage applied to the gateelectrode 250 offsets the negative charges to allow the 2DEG layer 215to return to a conduction mode. Therefore, a normally-off HFET device isachieved without degrading the electron mobility.

FIG. 4 is a partial/cross sectional perspective view to show analternate embodiment of a HFET power device 100′ of this invention. TheHFET power device 100′ is similar in structure as that shown in FIG. 1.The HFET power device 100′ includes three AlGaN/GaN hetero-junctionsbetween two layers of GaN layers 110-1 and 110-2 and two layers of AlGaNlayers 120-1 and 120-2 respectively thus forming three channels of 2DEGlayers (not specifically shown but the same as FIGS. 1-3)—one 2DEGchannel at each of the AlGaN/GaN hetero-junctions. The gate electrode150′ is insulated from the negative charged floating gate 160′ with athick oxide layer 155′. The negatively charged floating gate 160′surrounds the hetero-junctions on both the top and on both sides of thehetero-junctions formed between the GaN and AlGaN layers. A wrap-aroundconfiguration of the negatively charged floating gate 160′ would furtherassure complete depletion of the channels thus reliably providing anormally-off multi-channel HFET power device 100′ with increasedelectric current flows between the source electrode 130′ (not shown inFIG. 4) to the drain electrode 140′, due to the multiple channelsprovided by the AlGaN/GaN layers 110-1, 120-1, 110-2, 120-2. FIG. 4shows a cross section to illustrate the gate and channel structure ofthe HFET power device 100′. FIG. 5 shows a top view of HFET power device100′ to illustrate the relative positioning of the source electrode130′, gate electrode 150′ and drain electrode 140′.

FIG. 6 shows a partial perspective view to show an alternativeembodiment of a HFET power device 100-1′. It is similar to HFET powerdevice 100′ of FIGS. 4 and 5, except that the two layers of GaN layers110-1 and 110-2 and two layers of AlGaN layers 120-1 and 120-2 of HFETpower device 100′ are replaced with just a single layer of GaN 110-1′and a single layer of AlGaN 120-1′. The HFET power device 100-1′ hasonly a single 2DEG channel disposed between the AlGaN layer 120-1′ andthe GaN layer 110-1′, but the floating gate 145′ is still wrapped aroundto improve control of the hetero-junction.

FIG. 7 shows a partial perspective view to show an alternativeembodiment of a HFET power device 100-2′. It is similar to HFET powerdevice 100′ of FIGS. 5 and 6, except that the two layers of GaN layers110-1 and 110-2 and two layers of AlGaN layers 120-1 and 120-2 of HFETpower device 100′ are replaced with two vertical layers of GaN layers110-1″ and 110-2″ and two vertical layers of AlGaN layers 120-1″ and120-2″. The vertically oriented layers mean that the hetero-junctionsGaN/AlGaN are vertically oriented and thus the 2DEG channels arevertically oriented as well. In this case the wrap-around floating gate160′ may be more effective in pinching off the 2DEG channels.

According to above drawings and descriptions, the present inventiondiscloses a method of forming a heterostructure field effect transistor(HFET) gallium nitride (GaN) semiconductor power device. The methodincludes steps of forming a hetero-junction structure from a firstsemiconductor layer interfacing a second semiconductor layer havingdifferent band gaps to make a two dimensional gas (2DEG) at thehetero-junction; forming a source electrode and drain electrode onopposite ends of the 2DEG; forming a floating gate over a portion of the2DEG, between the source and drain electrodes; and forming a gateelectrode over the floating gate, the gate electrode being insulatedfrom the floating gate by an insulating layer; wherein the floating gateis charged such that it depletes the 2DEG so that the device HFETsemiconductor device is normally off, and wherein the gate electrodecancels the charge of the floating gate to turn the device on. Inanother embodiment, the step of forming a hetero-junction structure froma first semiconductor layer comprising GaN interfacing a secondsemiconductor layer comprising Aluminum gallium nitride (AlGaN). Inanother embodiment, the method further includes a step of forming thefloating gate with a built-in negative charge. In another embodiment,the method further includes a step of forming the floating gate withnegative charge includes a step of writing the negative charges into thefloating gate in a similar manner as charge is written to flash memory.In another embodiment, the method further includes a step of wrappingthe floating gate and gate electrode around the sidewalls and top of thehetero-junction structure. In another embodiment, the method furtherincludes a step of insulating the floating gate from the hetero-junctionstructure with a thin insulating layer.

Although the present invention has been described in terms of thepresently preferred embodiment, it is to be understood that suchdisclosure is not to be interpreted as limiting. Various alterations andmodifications will no doubt become apparent to those skilled in the artafter reading the above disclosure. Accordingly, it is intended that theappended claims be interpreted as covering all alterations andmodifications as fall within the true spirit and scope of the invention.

What is claimed is:
 1. A heterostructure field effect transistor (HFET)gallium nitride (GaN) semiconductor power device comprising: ahetero-junction structure comprises a first semiconductor layerinterfacing a second semiconductor layer of two different band gaps thusgenerating an interface layer as a two-dimensional electron gas (2DEG)layer a floating gate wrapping around a segment of the hetero-junctionstructure disposed between a source electrode and a drain electrodedisposed on top of the hetero-junction structure; and a gate electrodewrapping around the floating gate for controlling a current flow betweensaid source and drain electrodes in said 2DEG layer.
 2. The HFET GaNsemiconductor power device of claim 1 wherein: the first semiconductorlayer comprising GaN interfacing the second semiconductor layercomprising Aluminum gallium nitride (AlGaN).
 3. The HFET GaNsemiconductor power device of claim 1 wherein: the floating gate havinga built-in negative charge.
 4. The HFET GaN semiconductor power deviceof claim 1 wherein: the HFET gallium nitride (GaN) semiconductor powerdevice is supported on a sapphire substrate for supporting thehetero-junction structure thereon.
 5. The HFET GaN semiconductor powerdevice of claim 1 wherein: the floating gate having a negatively chargedpotential to shift the pinch off voltage of the 2DEG layer from anegative pinch off voltage to a positive pinch off voltage equal to orgreater than three volts (3.0V).
 6. The HFET GaN semiconductor powerdevice of claim 1 wherein: the source electrode having an extended fieldplate extending from the source electrode and covering over the gateelectrode.
 7. The HFET GaN semiconductor power device of claim 1wherein: the source electrode further having an extended field plateextending from the source electrode and covering over the gate electrodewherein the field plate is insulated from the gate electrode with athick insulation layer.
 8. A method of forming a heterostructure fieldeffect transistor (HFET) gallium nitride (GaN) semiconductor powerdevice comprising: forming a hetero-junction structure from a firstsemiconductor layer interfacing a second semiconductor layer havingdifferent band gaps to make a two dimensional gas (2DEG) at thehetero-junction; forming a source electrode and drain electrode onopposite ends of the 2DEG; forming a floating gate wrapping around asegment of the hetero-junction structure between the source electrodeand the drain electrode on top of the hetero-junction structure; andforming a gate electrode wrapping around the floating gate forcontrolling a current flow between said source and drain electrodes insaid 2DEG layer.
 9. The method of claim 8 wherein: the step of formingthe hetero-junction structure further comprises a step of forming thefirst semiconductor layer comprising GaN interfacing the secondsemiconductor layer comprising Aluminum gallium nitride (AlGaN).
 10. Themethod of claim 8 wherein: the step of charging the gate insulationlayer to deplete the 2DEG further comprises a step of forming the gateinsulation layer with a built-in negative charge.
 11. The method ofclaim 8 further comprising: forming the HFET gallium nitride (GaN)semiconductor power device on a sapphire substrate for supporting thehetero-junction structure thereon.
 12. The method of claim 8 furthercomprising: forming a gate insulation layer between the gate electrodeand the hetero-junction structure and charging the gate insulation layerto deplete the 2DEG for operating the HFET semiconductor device in anormally off condition.
 13. The method of claim 12 wherein: the step ofcharging the gate insulation layer to deplete the 2DEG further comprisesa step of writing negative charges into said gate by insulation layer byapplying a similar process of writing charges to a floating gate of aflash memory.
 14. The method of claim 12 wherein: the process of formingthe gate insulation layer further comprises a step of forming the gateinsulation layer with the negatively charged potential to shift thepinch off voltage of the 2DEG layer from a negative pinch off voltage toa positive pinch off voltage equal to or greater than three volts(3.0V).
 15. The method of claim 8 wherein: the step of forming thesource electrode further includes a step of forming the source electrodewith an extended field plate extending from the source electrode andcovering over the gate electrode.
 16. The method of claim 8 wherein: thestep of forming the source electrode further includes a step of formingan extended field plate extending from the source electrode and coveringover the gate electrode wherein the field plate is insulated from thegate electrode with a thick insulation layer.